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Machine Intelligence Using Hierarchical Memory Networks
Abstract
This chapter presents the fundamentals of a hardware based memory network that can perform complex cognitive tasks. The network is designed to provide space dimensionality reduction, which enables desired functionality in a random environment. Complex network functionality is achieved by simple network cells that minimize the needed chip area for hardware implementation. Functionality of this network is demonstrated by automatic character recognition with various input deformations. In the character recognition, the network is trained to recognize characters deformed by random noise, rotation, scaling, and shifting. This example demonstrates how cognitive functionality of a hardware network can be achieved through an evolutionary process, as distinct from design based on mathematical formalism.
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