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Information Resources Management Association
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Implementation of FFT on General-Purpose Architectures for FPGA

Implementation of FFT on General-Purpose Architectures for FPGA
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Author(s): Fabio Garzia (Tampere University of Technology, Finland), Roberto Airoldi (Tampere University of Technology, Finland) and Jari Nurmi (Tampere University of Technology, Finland)
Copyright: 2012
Pages: 19
Source title: Computer Engineering: Concepts, Methodologies, Tools and Applications
Source Author(s)/Editor(s): Information Resources Management Association (USA)
DOI: 10.4018/978-1-61350-456-7.ch310


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This paper describes two general-purpose architectures targeted to Field Programmable Gate Array (FPGA) implementation. The first architecture is based on the coupling of a coarse-grain reconfigurable array with a general-purpose processor core. The second architecture is a homogeneous multi-processor system-on-chip (MP-SoC). Both architectures have been mapped onto two different Altera FPGA devices, a StratixII and a StratixIV. Although mapping onto the StratixIV results in higher operating frequencies, the capabilities of the device are not fully exploited. The implementation of a FFT on the two platforms shows a considerable speed-up in comparison with a single-processor reference architecture. The speed-up is higher in the reconfigurable solution but the MP-SoC provides an easier programming interface that is completely based on C language. The authors’ approach proves that implementing a programmable architecture on FPGA and then programming it using a high-level software language is a viable alternative to designing a dedicated hardware block with a hardware description language (HDL) and mapping it on FPGA.

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