SOI Technology in Designing Low-Power VLSI Circuits

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Author(s): Srividya P. (RV College of Engineering, India)
Copyright: 2023
Pages: 12
Source title: Energy Systems Design for Low-Power Computing
Source Author(s)/Editor(s): Rathishchandra Ramachandra Gatti (Sahyadri College of Engineering and Management, India), Chandra Singh (Sahyadri College of Engineering and Management, India), Srividya P. (RV College of Engineering, India)and Sandeep Bhat (Sahyadri College of Engineering and Management, India)
DOI: 10.4018/978-1-6684-4974-5.ch002

Keywords: Computer Engineering / Energy / Engineering Science Reference / Science & Engineering

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Abstract

At present, the transistor size is reduced to a few tens of nanometers, as larger transistors demand a large die area and power. Power is an important design parameter in multi-gigahertz communication and ASIC/SOC designs. To deliver higher performance with lower power, various technologies are adopted in semiconductor industry. SOI is one such technology that helps in achieving higher performance. It offers a platform to integrate digital and RF circuit onto a single chip. Adopting SOI technology, faster chips with lesser power can be designed. This extends the battery life of handheld devices. The SOI structure is comparable to MOSFET except for an added buried oxide (Box) layer beneath the device region. The Box layer isolates the top and the base silicon layers and reduces the junction capacitances. This reduction accelerates the speed, lowers the power consumption, allows higher transistor stacking, and improves the device performance. These capabilities have led SOI usage in RF circuits. This chapter discusses the SOI technology in building energy- and power-efficient designs.

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