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Dynamic Body Bias: A Transistor-Level Technique for the Design of Low-Voltage CMOS Analog Circuits
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Author(s): Vandana Niranjan (Indira Gandhi Delhi Technical University for Women, India)
Copyright: 2023
Pages: 23
Source title:
Energy Systems Design for Low-Power Computing
Source Author(s)/Editor(s): Rathishchandra Ramachandra Gatti (Sahyadri College of Engineering and Management, India), Chandra Singh (Sahyadri College of Engineering and Management, India), Srividya P. (RV College of Engineering, India)and Sandeep Bhat (Sahyadri College of Engineering and Management, India)
DOI: 10.4018/978-1-6684-4974-5.ch004
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Abstract
The demand for portable device applications has grown immensely. For such applications, low voltage and low power operation is an essential prerequisite to prevent overheating and ensure reliable functioning. Low voltage operation curtails the total number, weight, and dimensions of batteries, and low power consumption extends battery life. The shrinking size of MOS transistors in CMOS processes necessitates the use of lower supply voltages. Since the threshold voltage of MOS transistor is not diminished at the same rate as the power supply voltage, analog designers face problems due to shrinking voltage headroom. One of the findings that can overcome the issues introduced by comparably high threshold voltages is based on the enactment of body bias approach. In such a solution, a relatively small potential is applied at body terminal of a MOS transistor to adjust its threshold voltage. This chapter discussed that body bias approach is an attractive opportunity for utilizing the body effect positively to improve the performance of low voltage-integrated circuits.
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