System-Level Analysis of MPSoCs with a Hardware Scheduler

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Author(s): Diandian Zhang (RWTH Aachen University, Germany), Jeronimo Castrillon (Dresden University of Technology, Germany), Stefan Schürmans (RWTH Aachen University, Germany), Gerd Ascheid (RWTH Aachen University, Germany), Rainer Leupers (RWTH Aachen University, Germany)and Bart Vanthournout (Synopsys Inc., Belgium)
Copyright: 2016
Pages: 36
Source title: Leadership and Personnel Management: Concepts, Methodologies, Tools, and Applications
Source Author(s)/Editor(s): Information Resources Management Association (USA)
DOI: 10.4018/978-1-4666-9624-2.ch035

Keywords: Administration & Leadership / Business & Management / Business Science Reference / Management Science

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Abstract

Efficient runtime resource management in heterogeneous Multi-Processor Systems-on-Chip (MPSoCs) for achieving high performance and energy efficiency is one key challenge for system designers. In the past years, several IP blocks have been proposed that implement system-wide runtime task and resource management. As the processor count continues to increase, it is important to analyze the scalability of runtime managers at the system-level for different communication architectures. In this chapter, the authors analyze the scalability of an Application-Specific Instruction-Set Processor (ASIP) for runtime management called OSIP on two platform paradigms: shared and distributed memory. For the former, a generic bus is used as interconnect. For distributed memory, a Network-on-Chip (NoC) is used. The effects of OSIP and the communication architecture are jointly investigated from the system point of view, based on a broad case study with real applications (an H.264 video decoder and a digital receiver for wireless communications) and a synthetic benchmark application.

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System-Level Analysis of MPSoCs with a Hardware Scheduler

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