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An Integrated Framework to Simulate SysML Models Using DEVS Simulators
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Author(s): G.-D. Kapos (Harokopio University of Athens, Greece), V. Dalakas (Harokopio University of Athens, Greece), M. Nikolaidou (Harokopio University of Athens, Greece)and D. Anagnostopoulos (Harokopio University of Athens, Greece)
Copyright: 2014
Pages: 28
Source title:
Formal Languages for Computer Simulation: Transdisciplinary Models and Applications
Source Author(s)/Editor(s): Pau Fonseca i Casas (Universitat Politècnica de Catalunya - BarcelonaTech, Spain)
DOI: 10.4018/978-1-4666-4369-7.ch010
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Abstract
System models validation is an important engineering activity of the system development life-cycle, usually performed via simulation. However, usability and effectiveness of many validation approaches are hindered by the fact that system simulation is not performed using a system model described by a standardized modeling language as SysML. This requires system simulation models to be recreated from scratch, burdening the engineer and introducing inconsistencies between system and validation models. In this chapter, the authors present how system engineers may effectively perform SysML system model validation utilizing the original SysML model and standards-based simulated related extensions. This is achieved by a framework that exploits MDA concepts and techniques, such as profiling, meta-modeling, and formal transformations. This way an open, standards-based, customizable approach for SysML models validation using DEVS simulators is formed. A simple battle system is used as an example throughout the chapter to facilitate the presentation of the proposed approach.
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