Power Optimization Using Clock Gating and Power Gating: A Review

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Author(s): Arsalan Shahid (HITEC University, Pakistan), Saad Arif (HITEC University, Pakistan), Muhammad Yasir Qadri (University of Essex, UK)and Saba Munawar (COMSATS Institute of Information Technology, Pakistan)
Copyright: 2016
Pages: 20
Source title: Innovative Research and Applications in Next-Generation High Performance Computing
Source Author(s)/Editor(s): Qusay F. Hassan (Mansoura University, Egypt)
DOI: 10.4018/978-1-5225-0287-6.ch001

Keywords: Computer Science & IT / Engineering Science Reference / Grid & High Performance Computing / High Performance Computing

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Abstract

The scaling of CMOS technology has continued due to ever increasing demand of greater performance with low power consumption. This demand has grown further by the portable and battery operated devices market. To meet the challenge of greater energy efficiency and performance, a number of power optimization techniques at processor and system components level are proposed by the research community such as clock gating, operand isolation, memory splitting, power gating, dynamic voltage and frequency scaling, etc. This chapter reviews advancements in the dynamic power optimization techniques like clock gating and power gating. This chapter also reviews some architectures and optimization techniques that have been developed for greater power reduction without any significant performance degradation or area cost.

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Power Optimization Using Clock Gating and Power Gating: A Review

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