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High-Performance Image Reconstruction (HPIR) in Three Dimensions
Abstract
Commonly used in medical imaging for diagnostic purposes, in luggage scanning, as well as in industrial non-destructive testing applications, Computed Tomography (CT) is an imaging technique that provides cross sections of an object from measurements taken from different angular positions around the object. CT, also referred to as Image Reconstruction (IR), is known to be a very compute-intensive problem. In its simplest form, the computational load is a function of O(M × N3), where M represents the number of measurements taken around the object and N is the dimension of the object. Furthermore, research institutes report that the increase in processing power required by CT is consistently above Moore‘s Law. On the other hand, the changing work flow in hospital requires obtaining CT images faster with better quality from lower dose. In some cases, real time is needed. High Performance Image Reconstruction (HPIR) has to be used to match the performance requirements involved by the use of modern CT reconstruction algorithms in hospitals. Traditionally, this problem had been solved by the design of specific hardware. Nowadays, the evolution of technology makes it possible to use Components of the Shelf (COTS). Typical HPIR platforms can be built around multicore processors such as the Cell Broadband Engine (CBE), General-Purpose Graphics Processing Units (GPGPU) or Field Programmable Gate Arrays (FPGA). These platforms exhibit different level in the parallelism required to implement CT reconstruction algorithms. They also have different properties in the way the computation can be carried out, potentially requiring drastic changes in the way an algorithm can be implemented. Furthermore, because of their COTS nature, it is not always easy to take the best advantages of a given platform and compromises have to be made. Finally, a fully fleshed reconstruction platform also includes the data acquisition interface as well as the vizualisation of the reconstructed slices. These parts are the area of excellence of FPGAs and GPGPUs. However, more often then not, the processing power available in those units exceeds the requirement of a given pipeline and the remaining real estate and processing power can be used for the core of the reconstruction pipeline. Indeed, several design options can be considered for a given algorithm with yet another set of compromises.
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