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CNTFET for Logic Gates Design

CNTFET for Logic Gates Design
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Author(s): Gurmohan Singh (Centre for Development of Advanced Computing, India), Manjit Kaur (Centre for Development of Advanced Computing, India) and Yadwinder Kumar (Yadavindra College of Engineering, Punjabi University, India)
Copyright: 2020
Pages: 18
Source title: Major Applications of Carbon Nanotube Field-Effect Transistors (CNTFET)
Source Author(s)/Editor(s): Balwinder Raj (National Institute of Technical Teachers Training and Research, Chandigarh, India), Mamta Khosla (Dr. B. R. Ambedkar National Institute of Technology, Jalandhar, India) and Amandeep Singh (National Institute of Technology, Srinagar, India)
DOI: 10.4018/978-1-7998-1393-4.ch004

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Abstract

The novel characteristics of CNTFET have eliminated many technological and fundamental hindrances being faced by CMOS transistors. CNTFET is emerging as prospective replacement for CMOS transistors in digital circuits and systems. This chapter introduces design of CNTFET-based basic logic gates. The basic logic gates analyzed are inverter, NAND, and NOR gates. The designed gates are evaluated in terms of delay, power consumption, and figure-of-merit power-delay-product (PDP). The standard H-SPICE CNTFET model of Stanford University has been used for all simulations. The impact of dielectric material variations on performance parameters of carbon nanotube field effect transistor based universal gates has been analyzed. Comparison between CMOS and CNTFET-based logic circuits is carried out for different dielectric material at 16 nm technology node.

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