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Low Power, High Performance CNTFET-Based SRAM Cell Designs: Design and Analysis of 6T CNTFET SRAM Cells
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Author(s): B. K. Madhavi (Siddhartha Institute of Engineering and Technology, Hyderabad, India)and Rajendra Prasad Somineni (Vallurupalli Nageswara Rao Vignana Jyothi Institute of Engineering and Technology, Hyderabad, India)
Copyright: 2020
Pages: 36
Source title:
Major Applications of Carbon Nanotube Field-Effect Transistors (CNTFET)
Source Author(s)/Editor(s): Balwinder Raj (National Institute of Technical Teachers Training and Research, Chandigarh, India), Mamta Khosla (Dr. B. R. Ambedkar National Institute of Technology, Jalandhar, India)and Amandeep Singh (National Institute of Technology, Srinagar, India)
DOI: 10.4018/978-1-7998-1393-4.ch006
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Abstract
The main objective of this chapter is to provide high-performance, low-power solutions for VLSI system designers. As technology scales down to 32nm and below, the present CMOS technology has to face the scaling limit, such as the increased leakage power, SCEs, and so on. To overcome these limits, the researchers have experimented on other technologies, among which a CNT technology-based device called CNTFET has been evaluated as one of the promising replacements to CMOS technology. In any digital systems, memory is an integral part, and it is also the largest constituent. SRAM is a widely used memory. In today's ICs, SRAM is going to occupy 60-70% of the total chip area. In this connection, this chapter describes the design of CNTFET-based 6T SRAM cell using circuit-level leakage reduction techniques, named sleep transistor, forced stack, data-retention sleep transistor, and stacked sleep.
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