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Low Complexity Processor Designs for Energy-Efficient Security and Error Correction in Wireless Sensor Networks
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Author(s): J. H. Kong (The University of Nottingham- Malaysia Campus, Malaysia), J. J. Ong (The University of Nottingham- Malaysia Campus, Malaysia), L.-M. Ang (The University of Nottingham- Malaysia Campus, Malaysia)and K. P. Seng (The University of Nottingham- Malaysia Campus, Malaysia)
Copyright: 2012
Pages: 19
Source title:
Wireless Sensor Networks and Energy Efficiency: Protocols, Routing and Management
Source Author(s)/Editor(s): Noor Zaman (King Faisal University, Saudi Arabia), Khaled Ragab (King Faisal University, Saudi Arabia)and Azween Bin Abdullah (Universiti Teknologi Petronas, Malaysia)
DOI: 10.4018/978-1-4666-0101-7.ch017
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Abstract
This chapter presents low complexity processor designs for energy-efficient security and error correction for implementation on wireless sensor networks (WSN). WSN nodes have limited resources in terms of hardware, memory, and battery life span. Small area hardware designs for encryption and error-correction modules are the most preferred approach to meet the stringent design area requirement. This chapter describes Minimal Instruction Set Computer (MISC) processor designs with a compact architecture and simple hardware components. The MISC is able to make use of a small area of the FPGA and provides a processor platform for security and error correction operations. In this chapter, two example applications, which are the Advance Encryption Standard (AES) and Reed Solomon (RS) algorithms, were implemented onto MISC. The MISC hardware architecture for AES and RS were designed and verified using the Handel-C hardware description language and implemented on a Xilinx Spartan-3 FPGA.
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