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Hardware Transactional Memories: A Survey
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Author(s): Arsalan Shahid (HITEC University, Pakistan), Maryam Murad (HITEC University, Taxila Cantt, Pakistan), Muhammad Yasir Qadri (University of Essex, UK), Nadia N. Qadri (COMSATS Institute of Information Technology, Pakistan)and Jameel Ahmed (HITEC University, Pakistan)
Copyright: 2016
Pages: 19
Source title:
Innovative Research and Applications in Next-Generation High Performance Computing
Source Author(s)/Editor(s): Qusay F. Hassan (Mansoura University, Egypt)
DOI: 10.4018/978-1-5225-0287-6.ch003
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Abstract
The initiation to have a concept of shared memory in processors has built an opportunity for thread level parallelism. In various applications, synchronization or ordering tools are utilized to have an access to shared data. Traditionally, multithreaded programming models usually suggest a set of low-level primitives, such as locks, to guarantee mutual exclusion. Possession of one or more locks protects access to shared data. But, due to some flaws they become a suboptimal solution. The idea of transactional memory is in research presently as an alternative to locks. Among which, one way is hardware transactional memory. Atomicity is well supported by using transactions in hardware. In this chapter, we have focused on hardware transactional memories and the work done on them so far.
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