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Functional Verification of ASICs for Performance Optimization in Front-End VLSI Design
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Author(s): Sabyasachi Mukhopadhyay (Sharda University, India), Vishal Jain (School of Engineering and Technology, Vivekananda Institute of Professional Studies, New Delhi, India), Pujari Lokesh (Sharda University, India)and Sachin Kumar (Sharda University, India)
Copyright: 2025
Pages: 38
Source title:
Exploring the Intricacies of Digital and Analog VLSI
Source Author(s)/Editor(s): Koushik Guha (National Institute of Technology, Silchar, India), Jyoti Kandpal (Graphic Era Hill University, Dehradun, India)and Swagata Devi (Faculty of Engineering, Assam Down Town University, India)
DOI: 10.4018/979-8-3693-8084-0.ch004
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Abstract
The designing of Application Specific Integrated Circuits (ASICs) starts with a behavioral description and ended up with commercial Integrated Circuits (ICs). The entire scenario is not that easy, rather involve several complex stages. The process carried out at the fabrication laboratories are referred as back end designing. The scope of this chapter involves designing of several digital modules which are combinational in nature and are very useful for designing several ASICs of modern-day use. The implementations have been carried out using Proteus. Software called Proteus is used to design, sketch, and combine electronic circuits. Finally, performance optimization has been achieved in terms of delay, hardware complexities and energy efficiency in case of designing approximate adder. Approximate adder finds its role in several domain such as digital signal processing, machine learning interface, cryptographic hush function, approximate computing and real time control system.
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