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Detailed Analysis of Ultra Low Power Column Compression WALLACE and DADDA Multiplier in Sub-Threshold Regime
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Author(s): Priya Gupta (BITS, India), Anu Gupta (BITS, India)and Abhijit Asati (BITS, India)
Copyright: 2016
Pages: 46
Source title:
Handbook of Research on Advanced Hybrid Intelligent Techniques and Applications
Source Author(s)/Editor(s): Siddhartha Bhattacharyya (RCC Institute of Information Technology, India), Pinaki Banerjee (Goldstone Infratech Limited, India), Dipankar Majumdar (RCC Institute of Information Technology, India)and Paramartha Dutta (Visva-Bharati University, India)
DOI: 10.4018/978-1-4666-9474-3.ch004
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Abstract
In this chapter, the design and comparative analysis is done in between the most well-known column compression multipliers by Wallace and Dadda in sub-threshold regime. In order to reduce the hardware which ultimately reduces area, power and overall power delay product, an energy efficient basic modules of the multipliers like AND gates, half adders, full adders and partial product generate units have been analyzed for sub-threshold operation. At the last stage ripple carry adder is used in both multipliers. The performance metrics considered for the analysis of the multipliers are: power, delay and PDP. Simulation studies are carried out for 8x8-bit and 16x16-bit input data width. The proposed circuits show energy efficient results with Spectre simulations for the TSMC 180nm CMOS technology at 0.4V supply voltage. The proposed multipliers so implemented outperform its counterparts exhibiting low power consumption and lesser propagation delay as compared to conventional multipliers.
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