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Design Time Engineering of Side Channel Resistant Cipher Implementations
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Author(s): Alessandro Barenghi (Politecnico di Milano, Italy), Luca Breveglieri (Politecnico di Milano, Italy), Fabrizio De Santis (Technische Universität München, Germany), Filippo Melzani (STMicroelectronics, Italy), Andrea Palomba (Politecnico di Milano, Italy)and Gerardo Pelosi (Politecnico di Milano, Italy)
Copyright: 2013
Pages: 25
Source title:
Theory and Practice of Cryptography Solutions for Secure Information Systems
Source Author(s)/Editor(s): Atilla Elçi (Hasan Kalyoncu University, Turkey), Josef Pieprzyk (Macquarie University, Australia), Alexander G. Chefranov (Eastern Mediterranean University, North Cyprus), Mehmet A. Orgun (Macquarie University, Australia), Huaxiong Wang (Nanyang Technological University, Singapore)and Rajan Shankaran (Macquarie University, Australia)
DOI: 10.4018/978-1-4666-4030-6.ch006
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Abstract
Dependable and trustworthy security solutions have emerged as a crucial requirement in the specification of the applications and protocols employed in modern Information Systems (IS). Threats to the security of embedded devices, such as smart phones and PDAs, have been growing since several techniques exploiting side-channel information leakage have proven successful in recovering secret keys even from complex mobile systems. This chapter summarizes the side-channel techniques based on power consumption and elaborates the issue of the design time engineering of a secure system, through the employment of the current hardware design tools. The results of the analysis show how these tools can be effectively used to understand possible vulnerabilities to power consumption side-channel attacks, thus providing a sound conservative margin on the security level. The possible extension of this methodology to the case of fault attacks is also sketched.
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