Cutting-Edge Methodologies for Low Power Design in VLSI Circuits

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Author(s): Uma Sharma (Ajay Kumar Garg Engineering College, India), Tukur Gupta (Ajay Kumar Garg Engineering College, India)and Neeti Bansal (Ajay Kumar Garg Engineering College, India)
Copyright: 2025
Pages: 38
Source title: Exploring the Intricacies of Digital and Analog VLSI
Source Author(s)/Editor(s): Koushik Guha (National Institute of Technology, Silchar, India), Jyoti Kandpal (Graphic Era Hill University, Dehradun, India)and Swagata Devi (Faculty of Engineering, Assam Down Town University, India)
DOI: 10.4018/979-8-3693-8084-0.ch002

Keywords: Computer Engineering / Engineering Science Reference / High Performance Computing / Science & Engineering

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Abstract

The rapid advancements in Very Large Scale Integration (VLSI) technology have been driven by the increasing demand for high-performance and energy-efficient electronic devices. Low power design has emerged as a critical focus area in modern electronic systems to address these demands. The chapter categorizes design approaches into conventional methods, such as static and dynamic CMOS technologies, and non-conventional techniques, including FinFET, Carbon Nanotube Field Effect Transistors (CNTFET), and Floating Gate MOSFET (FGMOS). A comparative analysis of XOR/XNOR circuits highlights their design characteristics, performance trade-offs, and challenges. The findings indicate that FGMOS technology offers superior power efficiency, while CNTFET technology significantly improves circuit speed at lower technological nodes. However, the adoption of non-conventional technologies is constrained by the lack of robust simulation models and the complexity of fabrication processes.

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Cutting-Edge Methodologies for Low Power Design in VLSI Circuits

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