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CNTFET-Based Ternary Logic Gates: Design and Analysis Approach

CNTFET-Based Ternary Logic Gates: Design and Analysis Approach
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Author(s): Suman Rani (I.K.G. Punjab Technical University Jalandhar, Punjab, India & Baba Farid College of Engineering and Technology, Bathinda, India.) and Balwinder Singh (ACS Division, Centre for Development of Advanced Computing, Mohali, India)
Copyright: 2020
Pages: 21
Source title: Major Applications of Carbon Nanotube Field-Effect Transistors (CNTFET)
Source Author(s)/Editor(s): Balwinder Raj (National Institute of Technical Teachers Training and Research, Chandigarh, India), Mamta Khosla (Dr. B. R. Ambedkar National Institute of Technology, Jalandhar, India) and Amandeep Singh (National Institute of Technology, Srinagar, India)
DOI: 10.4018/978-1-7998-1393-4.ch005


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In the recent digital designs, there are certain circumstances where energy efficiency and ease is required, and in such situations, ternary logic (or three-valued logic) is favored. Ternary logic is an auspicious supernumerary to the conventional binary (0, 1) logic design techniques as this one is possible to attain straightforwardness and energy efficiency. This chapter deals with the comparative analysis of CMOS and CNTFET-based ternary inverter and universal gates design. The simulation result is analyzed and validated with a Hailey simulation program with integrated circuit (HSPICE) simulations. The average delay and power consumption in CNTFET-based ternary inverter have been reduced by approximately 90.3% and 48.8% respectively, as compared to CMOS-based ternary inverter design. Likewise, delay is reduced by 50% and power gets 99% reduction in ternary CNTFET NAND gate as compared to CMOS-based ternary NAND gat. It is concluded that CNFETs are faster and consume less power compared to CMOS technology.

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