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Performance Analysis of FPGA Architectures based Embedded Control Applications
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Author(s): Slim Ben Othman (National Institute of Applied Sciences and Technology (INSAT), Tunisia), Ahmed Karim Ben Salem (National Institute of Applied Sciences and Technology (INSAT), Tunisia)and Slim Ben Saoud (National Institute of Applied Sciences and Technology (INSAT), Tunisia)
Copyright: 2011
Pages: 37
Source title:
Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility
Source Author(s)/Editor(s): Mohamed Khalgui (Xidian University, China)and Hans-Michael Hanisch (Martin Luther University, Germany)
DOI: 10.4018/978-1-60960-086-0.ch011
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Abstract
The performances of System on Chip (SoC) and the Field Programmable Gate Array (FPGA) particularly, are increasing continually. Due to the growing complexity of modern embedded control systems, the need of more performance digital devices is evident. Recent FPGA technology makes it possible to include processor cores into the FPGA chip, which ensures more flexibility for digital controllers. Indeed, greater functionality of hardware and system software, Real-Time (RT) platforms and distributed subsystems are demanded. In this chapter, a design concept of FPGA based controller with Hardware/Software (Hw/Sw) codesign is proposed. It is applied for electrical machine drives. There are discussed different MultiProcessor SoC (MPSoC) architectures with Hw peripherals for the implementation on FPGA-based embedded processor cores. Hw accelerators are considered in the design to enhance the controller speed performance and reduce power consumption. Test and validation of this control system are performed on a RT motor emulator implemented on the same FPGA. Experimental results, carried on a real prototyping platform, are given in order to analyze the performance and efficiency of discussed architecture designs helping to support hard RT constraints.
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