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Hardware Virtualization on Dynamically Reconfigurable Processors
Abstract
Numerous research efforts in reconfigurable embedded processors have shown that augmenting a CPU core with a coarse-grained reconfigurable array for application-specific hardware acceleration can greatly increase performance and energy-efficiency. The traditional execution model for such reconfigurable co-processors however requires the accelerated function to fit onto the reconfigurable array as a whole, which restricts the applicability to rather small functions. In the authors’ research presented in this chapter, the authors have studied hardware virtualization approaches that overcome this restriction by leveraging dynamic reconfiguration. They present two different hardware virtualization methods, virtualized execution and temporal partitioning, and introduce the Zippy reconfigurable processor architecture that has been designed with specific hardware virtualization support. Further, the authors outline the corresponding hardware and software tool flows. Finally, the authors demonstrate the potential provided by hardware virtualization with two case studies and discuss directions for future research.
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