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FPGA-Based Re-Configurable Architecture for Window-Based Image Processing
Abstract
In this proposed book chapter, a simple but efficient presentation of Median Filter, Switching Median Filter, Adaptive Median Filter and Decision-Based Adaptive Filtering Method and their hardware architecture for FPGA is described for removal of up to 99% impulse noise from Digital Images. For hardware architecture, simulation is done using Xilinx ISE 14.5 software of XILINX. For implementation, these approaches utilize Genesys VIRTEX V FPGA device of XC5VLX50T device family. In this approach, we proposed an efficient design for suppression of impulse noise from digital images corrupted by up to 99% impulse noise using decision based adaptive filtering method as well as preserve the details of image. The method works in two different stages – noise detection using switching technique and finally noise suppression and restoration. Experimental results show that our method perform better in terms of PSNR below 80% noise density but above 80% noise density it is almost comparable with the latest methods.
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